View MX30LF1G08AA-XKI_8809617.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 mx30lf1g08aa 1g-bit nand flash memory p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
2 contents 1. features ........................................................................................................................................ 4 2. general descriptions ............................................................................................................. 4 figure 1. logic diagram ......................................................................................................................... 4 2-1. ordering information ................................................................................................... 5 3. pin configurations ................................................................................................................... 6 3-1. pin descriptions ............................................................................................................... 7 4. pin functions ............................................................................................................................... 8 5. block diagram ............................................................................................................................ 9 figure 2. ac waveform for command / address / data latch timing ................................................. 10 figure 3. ac waveforms for address input cycle ................................................................................ 10 6. device operations ................................................................................................................... 10 figure 4. ac waveforms for command input cycle ............................................................................ 11 figure 5. ac waveforms for data input cycle ..................................................................................... 11 figure 6. ac waveforms for read cycle ............................................................................................. 12 figure 7. ac waveforms for read operation (intercepted by ce#) .................................................... 13 figure 8. read operation with ce# don't care ................................................................................... 14 figure 9. ac waveforms for sequential data out cycle (after read) ................................................. 14 figure 10. ac waveforms for random data output ............................................................................ 15 figure 11. ac waveforms for cache read .......................................................................................... 17 figure 12. ac waveforms for program operation after command 80h .............................................. 18 figure 13. ac waveforms for random data in (for page program) ................................................... 19 figure 14. program operation with ce# don't care ............................................................................ 20 figure 15-1. ac waveforms for cache program ................................................................................. 22 figure 15-2. sequence of cache program ......................................................................................... 23 figure 16. ac waveforms for erase operation .................................................................................... 24 figure 17. ac waveforms for id read operation ................................................................................ 25 figure 18. ac waveforms for status read operation ......................................................................... 26 figure 19. reset operation .................................................................................................................. 27 7. parameters ................................................................................................................................ 28 7-1. absolute maximum ratings ....................................................................................... 28 figure 20. device under test ............................................................................................................... 30 table 1. operating range .................................................................................................................... 29 table 2. dc characteristics .................................................................................................................. 29 table 3. capacitance ............................................................................................................................ 29 p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
3 table 4. ac testing conditions ............................................................................................................ 30 table 5. program, read and erase characteristics ............................................................................. 30 table 6. ac characteristics over operating range .............................................................................. 31 8. schematic cell layout and address assignment ...................................................... 32 table 7. address allocation .................................................................................................................. 32 9. operation modes: logic and command t ables ............................................................ 33 figure 21. bit assignment (hex data) ................................................................................................. 34 table 8. logic table ............................................................................................................................. 33 table 9. hex command table ............................................................................................................. 34 table 10. status output ........................................................................................................................ 35 table 11. id codes read out by id read command 90h .................................................................. 35 table 12. the defnition of 3rd code of id table ................................................................................ 36 table 13. the defnition of 4th code of id table ................................................................................. 36 9-1. r/b#: termination for the ready/busy# pin (r/b#) ............................................. 37 figure 22. r/b# pin timing information ............................................................................................... 37 9-2. power on/off sequence ............................................................................................. 38 figure 23. power on/off sequence ..................................................................................................... 38 figure 24. enable programming .......................................................................................................... 39 figure 25. disable programming ......................................................................................................... 39 figure 26. enable erasing .................................................................................................................... 39 figure 27. disable erasing ................................................................................................................... 39 10. software algorithm .............................................................................................................. 40 10-1. invalid blocks (bad blocks) ..................................................................................... 40 figure 28. bad blocks .......................................................................................................................... 40 table 14. valid blocks .......................................................................................................................... 40 10-2. bad block test flow ................................................................................................... 41 10-3. failure phenomena for read/program/erase operations ......................... 41 table 15. failure modes ....................................................................................................................... 41 10-4. program ............................................................................................................................ 42 figure 30. failure modes ..................................................................................................................... 42 figure 31. program flow chart ............................................................................................................ 42 10-5. erase .................................................................................................................................. 42 figure 32. erase flow chart ................................................................................................................ 43 figure 33. read flow chart ................................................................................................................. 43 11. package information ............................................................................................................. 45 12. revision history ...................................................................................................................... 47 p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
4 1g-bit (128 m x 8 bit) nand flash memory 1. features ? 1 gbit slc nand flash - 128 m x 8 bit - 64 k pages of (2,048+64) bytes each - 1k blocks of 64 pages each ? multiplexed command/address/data ? 4 mbyte user redundancy - 64 bytes attached to each page ? fast read access - first-byte latency: 25us - sequential read: 30ns/byte ? cache read support ? page program operation ? cache program - internal cache of (2,048+64) bytes ? program time: page program 250us (typ.) ? single voltage operation: 3.3v ? low power dissipation - max. 30ma active current (rd/pgm/ers) ? automatic sleep mode - 50ua (max) standby current ? block erase architecture - block size: (128k+4k) bytes per block - 1k blocks, 64 pages each - block erase time: 2ms (t yp.) hardware data protection: wp# pin multiple device status indicators - ready/busy (r/b#) pin - status register chip enable don't care - simplify system interface status register ? electronic signature (four cycles) ? high reliability - endurance: 100 k cycles (with 1-bit ecc per 528-byte) - data retention: 10 years ? wide temperature operating range: -40 c to +85 c package: - 48-tsop(i) (12mm x 20mm), - 63-ball 9mmx11mm vfbga - all packaged devices are rohs compliant & halogen-free. 2. general descriptions the mx30lf1g08aa is a 1gb slc nand flash memory device. its standard nand flash features and reliable quality make it most suitable for embedded system code and data storage usage. the mx30lf1g08aa is typically accessed in pages of 2,112 bytes, both for read and for program operations. the mx30lf1g08aa array is organized as 1024 blocks, which is composed by 64 pages of (2,048+64) byte in two nand strings structure with 32 serial connected cells in each string. each page has an additional 64 bytes for ecc and other purposes. the device has an on-chip buffer of 2,112 bytes for data load and access. the cache read operation of the mx30lf1g08aa eegfffxg sequential read of 30ns per byte. fast programming is supported, enabling page programming at a rate of 8mb/sec (approx.) the mx30lf1g08aa power consumption is 30 ma during all modes of operations (read/ program/erase), and 50ua in standby mode. figure 1. logic diagram ce# cle ale we# wp# re# io7 - io0 r/b# 1gb p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
5 part number organization vcc range package temperatur grade mx30lf1g08aa-ti x8 2.7v - 3.6 volt 48-tsop industrial (-40 to 85c) MX30LF1G08AA-XKI x8 2.7v - 3.6 volt 63-vfbga industrial (-40 to 85c) 2-1. ordering information part name description operating temperature: i: industrial (-40c to 85c) package type: t: 48tsop xk: 0.8mm ball pitch, 0.45mm ball size and 1.0mm height of vfbga package: rohs compliant and halogen-free generation (tech. code) a mode: a = die#: 1, ce#: 1, r/b#: 1, reserve: 0 mx 30 l f 1g 08 a a - t i x classification: f = slc + large block density: 1g = 1gbit voltage: l = 2.7v to 3.6v type: 30 = nand flash brand: mx option code: 08 = x8 reserve p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
6 3. pin configurations 48-tsop nc nc nc nc nc nc r/b# re# ce# nc nc vcc vss nc nc cle ale we# wp# nc nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 nc nc nc nc io7 io6 io5 io4 nc nc nc vcc vss dnu nc nc io3 io2 io1 io0 nc nc nc nc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 a b c d e f g h j k l m nc nc nc ale wp# vss ce# we# r/b# nc re# cle nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dnu nc nc nc nc nc nc nc nc nc nc vcc io0 nc io1 io2 io3 vcc io5 io7 vss io6 vss io4 nc nc nc nc nc nc nc nc nc nc nc nc 63-ball 9mmx11mm vfbga p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
7 3-1. pin descriptions symbol pin name io7 - io0 data i/o port ce# chip enable (active low) re# read enable (active low) we# write enable (active low) cle command latch enable ale address latch enable wp# write protect (active low) r/b# ready/busy (open drain) vss ground vcc power supply for device operation nc not connected internally dnu do not use (do not connect) p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
8 4. pin functions the mx30lf1g08aa device is a sequential access memory that utilizes multiplexing input of command/address/data. i/o port: io7 - io0 the io7 to io0 pins are for address/command input and data output to and from the device. chip enable: ce# the device goes into low-power standby mode when ce# goes high during a read operation and not at busy stage. the ce# goes low to enable the device to be ready for standard operation. when the ce# goes high, the device is deselected. however, when the device is at busy stage, the device will not go to standby mode when ce# pin goes high. read enable: re# the re# (read enable) allows the data to be output by a trea time after the falling edge of re#. the internal address counter is automatically increased by one at the falling edge of re#. write enable: we# when the we# goes low, the address/data/com - mand are latched at the rising edge of we#. command latch enable: cle the cle controls the command input. when the cle goes high, the command data is latched at the rising edge of the we#. address latch enable: ale the ale controls the address input. when the ale goes high, the address is latched at the rising edge of we#. write protect: wp# the wp# signal keeps low and then the memory will not accept the program/erase operation. the wp# pin is not latched by we# for ensuring of the data can be protected during power-on. it is recommended to keep wp# pin low during power on/off sequence. please refer to the waveform of "power on/off sequence". ready/busy: r/b# the r/b# is an open-drain output pin. the r/b# outputs the ready/busy status of read/program/ erase operation of the device. when the r/b# is at low, the device is busy for read or program or erase operation. when the r/b# is at high, the uhdgsurjudphudvhrshudwlrlvlvkhg please refer to section 9.1 for details. p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
9 5. block diagram io port control logic high voltage circuit address counter data buffer memory array x-dec page buffer y-dec cle ale ce# we# re# r/b# wp# io[7:0] p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
10 6. device operations address input / command input / data input address input bus operation is for address input to select the memory address. the command input bus operation is for giving command to the memory. the data input bus is for data input to the memory device. figure 2. ac waveform for command / address / data latch timing tcs tcls tals tch tclh tds tdh io[7:0] we# cle ale ce# twp / / / figure 3. ac waveforms for address input cycle io[7:0] cle ale ce# we# tcls twc twc twc twp twh twp twh twp twh tals tds tdh tds tdh tds tdh tds tdh twp talh a7-a0 a 11 -a8 a a 19 - 12 a 27 20 -a p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
11 figure 4. ac waveforms for command input cycle tcls tcs tclh tch twp tals talh tds tdh io[7:0] cle ale ce# we# figure 5. ac waveforms for data input cycle din0 din1 din2 dinn twp twh twp twh twp tals tds tds tdh tdh tds tdh tds tdh twp tch tclh twc io[7:0] cle ale ce# we# p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
12 figure 6. ac waveforms for read cycle io[x:0] cle ale ce# we# dout dout tcls tcs twc tclh tcls tclh talh tals tds tdh tds tdh tds tdh tds tdh tds tdh twb talh tr trr trea busy trc toh tchz re# r/b# tar tds tdh 00h 30h 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle page read :khqsrzhulvrqwkhghidxowvwdhriwkh11dvkphprulvdwuhdgprghvrwkhkfrppdqgffoh is not needed for the read operation. the mx30lf1g08aa array is accessed in page of 2,112 bytes. external reads begins after the r/b# pin goes to ready. the read operation may also be initiated by writing the 00h command and giving the address (column and urdgguhvvdgehljfruphgewkhkfrppdgwkh0;/)* ehjlvwkhlwhudouhdg operation and the chip enters busy state. the data can be read out in sequence after the chip is ready. refer to the waveform for read operation as below. to access the data in the same page randomly, a command of 05h may be written and only column address iroorljdgwkhfruphge(kfrppdg7khudgrpuhdgprghlvrwvxssruwhggxuljfdfkhuhdg operation. p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
13 figure 7. ac waveforms for read operation (intercepted by ce#) io[7:0] cle ale ce# we# dout n dout n+1 twb tr trc toh tchz re# r/b# 00h a7-a0 a11-a8 30h a19-a12 a27-a20 busy tar trr dout n+2 p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
14 figure 8. read operation with ce# don't care io[7:0] cle ale ce# we# data output (sequential) re# r/b# 00h start addr (4 cycles) 30h busy ce# don?t care note: the ce# "don't care" feature may simplify the system interface, which allows controller to directly download the code from fash device, and the ce# transitions will not stop the read operation during the latency time. figure 9. ac waveforms for sequential data out cycle (after read) io[7:0] ce# re# dout0 dout1 dout2 doutn trp treh tcea trea toh tchz trc trr trhz trp treh trp trea toh trhz trea toh trhz trp trhz toh r/b# p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
15 io[7:0] cle ale ce# we# dout m dout m+1 twb tr trc re# r/b# 00h a7-a0 a11-a8 30h a19-a12 a27-a20 busy tar trr io[7:0] cle ale ce# we# dout n dout n+1 re# r/b# 05h a7-a0 a11-a8 e0h tclr 05h trhw repeat if needed twhr trea a a figure 10. ac waveforms for random data output p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
16 cache read the cache read operation is for throughput enhancement by using the internal cache buffer. it allows automatic downloading of the consecutive pages and reading the entire fash memory , no additional dead time between pages or blocks. while the data is read out on one page, the data of next page can be read into the cache buffer. after writing the 00h command, the column and row address should be given for the start page selection. the address a[11:0] for the start page should be 000h. cache read begin command 31h should be issued to start the cache read operation. the random data out is not available for cache read operation. after the latency time tr, the data can be read out continuously. the user can check the chip status by the following method: - r/b# pin ("0" means the data is not ready, "1" means the user can read the data) - status register (sr[6] behaves the same as r/b# pin, sr[5] indicates the internal chip operation, "0" means the chip is in internal operation and "1" means the chip is idle.) status register can be checked after the read status command (70h) is issued. command 00h should be given to return to the cache read operation. to exit the cache read operation, the user needs to issue cache read end command (34h) or reset command. after the command is issued, the device will become idle within 5 us. p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
17 io[7:0] cle ale ce# we# page 1 twb tr trc re# r/b# 00h a7-a0 a11-a8 31h a19-a12 a27-a20 busy tar trr io[7:0] cle ale ce# we# re# r/b# 34h tclr a a dout 0 page 1 dout 1 page 1 dout 2111 page 2 dout 0 page 1 d out 2111 page 2 dout 0 page 2 dout 2111 page n dout 0 page n dout 2111 page repeat trcbsy figure 11. ac waveforms for cache read p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
18 page program the memory is programmed by page, which is 2,112 bytes. after program load command (80h) is issued and the row and column address is given, the data will be loaded into the chip sequentially. random data input command (85h) allows multi-data load in non-sequential address. after data load is complete, program confrm command (10h) is issued to start the page program operation. partial program in a page is allowed up to 4 times. however, the random data input mode for programming a page is allowed and number of times is not limited. the status of the program completion can be detected by r/b# pin or status register bit (io6). the program result is shown in the chip status bit (sr[0]). sr[0] = 1 indicates the page program is not successful and sr[0] = 0 means the program operation is successful. during the page program progressing, only the read status register command and reset command are accepted, others are ignored. figure 12. ac waveforms for program operation after command 80h io[7:0] cle ale ce# we# re# r/b# 80 h - a7- a0 - a27- a20 din 1 din n tcls tcs tclh twc tals tds tdh talh 10 h 70h status output twb tprog a11- a8 a19- a12 talh p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
19 figure 13. ac waveforms for random data in (for page program) io[7:0] cle ale ce# we# din a din a+n twc tprog re# r/b# 80h a7-a0 a11-a8 a19-a12 a27-a20 io[7:0] cle ale ce# we# 10h din b+m re# r/b# 85h a7-a0 a11-a8 din b 85h repeat if needed tadl twc tadl 70h status io0 = 0; pass io0 = 1; fail twb a a a7-a0 din a+n note: random data in is also supported in cache program. p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
20 figure 14. program operation with ce# don't care io[7:0] cle ale ce# we# data input 80h start add. (4 cycles) io[7:0] cle ale ce# we# data input 10h data input a a note: the ce# "don't care" feature may simplify the system interface, which allows the controller to directly write data into fash device, and the ce# transitions will not stop the program operation during the latency time. p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
21 cache program the cache program feature enhances the program performance by using the cache buffer of 2,112-byte. the serial data can be input to the cache buffer while the previous data stored in the buffer are programming into the memory cell. cache program command sequence is almost the same as page program command sequence. only the program confrm command (10h) is replaced by cache program command (15h). after the cache program command (15h) is issued. the user can check the status by the following methods. - r/b# pin - cache status bit (sr[6] = 0 indicates the cache is busy; sr[6] = 1 means the cache is ready). the user can issue another cache program command sequence after the cache is ready. the user can always monitor the chip state by ready/busy status bit (sr[5]). the user can issues either program confrm command (10h) or cache program command (15h) for the last page if the user monitor the chip status by issuing read status command (70h). however, if the user only monitors the r/b# pin, the user needs to issue the program confrm command (10h) for the last page. the user can check the pass/fail status through p/f status bit (sr[0]) and cache p/f status bit (sr[1]). sr[1] represents pass/fail status of the previous page. sr[1] is updated when sr[6] change from 0 to 1 or chip is ready. sr[0] shows the pass/fail status of the current page. it is updated when sr[5] change from "0" to "1" or the end of the internal programming. for more details, please refer to the related waveforms. p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
22 figure 15-1. ac waveforms for cache program io[x:0] cle ale ce# we# din din twc tcbsy tadl re# r/b# 80h busy 15h twb io[x:0] cle ale ce# we# din din tprog tadl re# r/b# 80h a11-a8 busy 10h twb note 70h status output a a 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle 4th address cycle 3rd address cycle 2nd address cycle 1st address cycle note: it indicates the last page input & program. p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
23 figure 15-2. sequence of cache program io[7:0] busy / r/b# 80h a7-a0 15h note 2 a11-a8 a19-a12 a27-a20 din din 80h a7-a0 15h a11-a8 a19-a12 a27-a20 din din 80h io[7:0] r/b# 80h a7-a0 15h a11-a8 a19-a12 a27-a20 din din 80h a7-a0 10h a11-a8 a19-a12 a27-a20 din din 70h a a tcbsy busy / tcbsy busy / tcbsy busy / tprog p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
24 figure 16. ac waveforms for erase operation block erase the mx30lf1g08aa supports a block erase command. this command will erase a block of 64 pages asso - ciated with the 10 most signifcant address bits (a27-a18). the completion of the erase operation can be detected by r/b# pin or status register bit (io6). recommend to check the status register bit io0 after the erase operation completes. during the erasing process, only the read status register command and reset command can be accepted, others are ignored. io[7:0] cle ale ce# we# re# r/b# 60h 70h stauts output tcls tcs tclh twc talh tals tds tdh tdh tds tdh tds d0h twb terase row address 1 row address p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
25 id read the device contains id codes that identify the device type and the manufacturer. the id read command sequence includes one command byte (90h), one address byte (00h). the read id command 90h may provide the manufacturer id (c2h) of one-byte and device id (f1h) of one-byte, also 3rd and 4th id code are followed. figure 17. ac waveforms for id read operation 00h c2h (note) 90h f1h (note) cle io[7:0] ale ce# we# re# tcls talh tals tar tdh trea toh tchz tds tcs note : also see table 12. id codes read out by id read command 90h . p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
26 status read the mx30lf1g08aa provides a status register that outputs the device status by writing a command code 70h, and then the io pins output the status at the falling edge of ce# or re# which occurs last. even though when multiple fash devices are connecting in system and the r/b#pins are common-wired, the two lines of ce# and re# may be checked for individual devices status separately. it is not required to toggle the ce# or re# for getting the status. the status read command 70h will keep the device at the status read mode unless next valid command is issued. the resulting information is outlined in table 11. figure 18. ac waveforms for status read operation cle 70h status output re# ce# we# io[7:0] tcls twhr twp tclr tds tdh tir trea tchz toh tcs tclh p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
27 reset the reset command ffh resets the read/program/erase operation and clear the status register to be e0h (when wp# is high). the reset command during the program/erase operation will result in the content of the selected locations(perform programming/erasing) might be partially programmed/erased. if the flash memory has already been set to reset stage with reset command, the additional new reset command is invalid. figure 19. reset operation io[7:0] cle ale we# trst re# r/b# ffh p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
28 temperature under bias -50 c to +125 c storage temperature -65 c to +150 c all input voltages with respect to ground (note 2) -0.6v to 4.6v vcc supply voltage with respect to ground (note 2) -0.6v to 4.6v esd protection >2000v all output voltages with respect to ground (note 2) -0.6v to 4.6v notes: 1. stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . 2. minimum voltage may undershoot to -2v for the period of time less than 20ns. 7. parameters 7-1. absolute maximum ratings p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
29 temperature vcc tolerance -40 c to +85 c +3.3 v 2.7 ~ 3.6 v table 2. dc characteristics ta = +25 c, f = 1 mhz symbol parameter typ. max. units conditions cin input capacitance 10 pf vin = 0 v cout output capacitance 10 pf vout = 0 v table 3. capacitance table 1. operating range symbol parameter test conditions min. typical max. unit vil input low level -0.3 0.2vcc v vih input high level 0.8vcc vcc+0.3 v vol output low voltage iol =2.1 ma, vcc=vcc min 0.4 v voh output high voltage ioh= -400ua, vcc=vcc min 2.4 v isb1 vcc standby current (cmos) ce# = vcc - 0.2 v, wp#= 0/vcc 10 50 ua isb2 vcc standby current (ttl) ce# = vih min, wp#= 0/vcc 1 ma icc1 vcc active current (sequential read) trc minimum ce#= vil, iout=0ma 15 30 ma icc2 vcc active current (program) 15 30 ma icc3 vcc active current (erase) 15 30 ma ili input leakage current vin = 0 to vcc max 10 ua ilo output leakage current vout = 0 to vcc max 10 ua ilo (r/b#) output current of r/b# pin vout = vol, vcc = vcc max 8 10 ma p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
30 figure 20. device under test table 5. program, read and erase characteristics 0v vcc test points vcc/2 output input vcc/2 device under test 3v 3.3k/ohm out c l c l = 50 pf 6.2k/ohm table 4. ac testing conditions testing conditions value unit input pulse level 0 to vcc v output load capacitance 1 ttl + cl (50) pf input rise and fall time 5 ns input timing measurement reference levels vcc/2 v output timing measurement reference levels vcc/2 v symbol parameter min. ty p . max. unit tprog page programming time 250 700 us tcbsy (program) dummy busy time for cache 4 700 us trcbsy (read) dummy busy time for cache read 5 us nop number of partial program cycles in same page 4 cycles terase (block) block erase time 2 3 ms p/e number of program/erase cycles per block 100,000 cycles p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
31 symbol parameter min. max. unit notes tcls cle setup time 15 - ns tclh cle hold time 5 - ns tcs ce# setup time 20 - ns tch ce# hold time 5 - ns twp write pulse width 15 - ns tals ale setup time 15 - ns talh ale hold time 5 - ns tds data setup time 5 - ns tdh data hold time 5 - ns twc write cycle time 30 - ns twh we# high hold time 10 - ns tadl last address latched to data loading time during program operations 100 - ns tww wp# transition to we# high 100 - ns trr read -to- re# falling edge 20 - ns trp read pulse width 15 - ns trc read cycle time 30 - ns trea re# access time (serial data access) - 20 ns tcea ce# access time - 25 ns toh data output hold time 10 - ns trhz re# -high-to-output-high impedance - 50 ns tchz ce#-high-to-output-high impedance - 50 ns treh re# -high hold time 10 - ns tir output-high-impedance-to- re# falling edge 0 - ns trhw re# high to we# low 0 - ns twhr we# high to re# low 60 - ns tr first byte latency - 25 us twb we# high to busy - 100 ns tclr cle low to re# low 15 - ns tar ale low to re# low 10 - ns trst device reset time (idle/read/program/erase) - 5/5/10/500 us note: a maximum 5us time is required for the device goes "busy" mode if the ffh (reset command) is setting at ready stage. table 6. ac characteristics over operating range p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
32 8. schematic cell layout and address assignment the mx30lf1g08aa array is organized as 1024 blocks, which is composed by 64 pages of (2,048+64)-byte in two nand strings structure with 32 serial connected cells in each string. each page has an additional 64 bytes for ecc and other purposes. the device has an on-chip buffer of 2,112 bytes for data load and access. each 2k-byte page has the two area, one is the main area which is 2048-bytes and the other is spare area which is 64-byte. there are four address cycles for the address allocation, please refer to table 7 . addresses io7 io6 io5 io4 io3 io2 io1 io0 column address - 1st cycle a7 a6 a5 a4 a3 a2 a1 a0 column address - 2nd cycle *l *l *l *l a11 a10 a9 a8 row address - 3rd cycle a19 a18 a17 a16 a15 a14 a13 a12 row address - 4th cycle a27 a26 a25 a24 a23 a22 a21 a20 table 7. address allocation note: io7 to io4 must be set to low in the second cycle. p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
33 9. operation modes: logic and command tables address input, command input and data input/output are managed by the cle, ale, ce#, we#, re# and wp# signals, as shown in table 8. program, erase, read and reset are four major operations modes controlled by command sets, please refer to table 9. notes: 1. h = vih; l = vil; x = vih or vil 2. wp# should be biased to cmos high or cmos low for stand-by . table 8. logic table mode ce# re# we# cle ale wp# address input (read mode) l h l h x address input (write mode) l h l h h command input (read mode) l h h l x command input (write mode) l h h l h data input l h l l h data output l h l l x during read (busy) x h h l l x during programming (busy) x x x x x h during erasing (busy) x x x x x h program/erase inhibit x x x x x l stand-by h x x x x 0v/vcc p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
34 the following is an example of a hex data bit assignment: figure 21. bit assignment (hex data) 0 1 1 1 0 0 0 0 sr7 6 5 4 3 2 1 sr0 status read: 70h caution : any undefned command inputs are prohibited except for above command set. first cycle second cycle acceptable while busy read mode 00h 30h random data input 85h - random data output 05h e0h cache read begin 00h 31h cache read end 34h v read id 90h - reset ffh - v page program 80h 10h cache program 80h 15h block erase 60h d0h read status 70h - v table 9. hex command table p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
35 pin s t a t u s related mode value sr[0] chip status page program, cache program (page n), block erase 0: passed 1: failed sr[1] cache program result cache program (page n-1) 0: passed 1: failed sr[2] - sr[4] not used sr[5] ready / busy ( for p/e/r controller) cache program/cache read operation, other page program/block erase/read are same as io6 0: busy 1: ready sr[6] ready / busy page program, block erase, cache program, read, cache read 0: busy 1: ready sr[7] write protect page program, block erase, cache program, read 0: protected 1: unprotected table 10. status output table 11. id codes read out by id read command 90h data io7 io6 io5 io4 io3 io2 io1 io0 hex maker code 1 1 0 0 0 0 1 0 c2h device code 1 1 1 1 0 0 0 1 f1h 3rd code 1 0 0 0 0 0 0 0 80h 4th code 0 0 0 1 1 1 0 1 1dh p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
36 table 12. the defnition of 3rd code of id table defnition information value die number 1 die io1, io0= 0,0 2 die io1, io0= 0,1 4 die io1, io0= 1,0 reserved io1, io0= 1,1 cell structure single level cell io3, io2= 0,0 2x mult-level cell io3, io2= 0,1 reserved io3, io2= 1,0 reserved io3, io2= 1,1 number of concurrently programmed pages 1 io5, io4= 0,0 2 io5, io4= 0,1 3 io5, io4= 1,0 4 io5, io4= 1,1 interleaved programming between diverse devices not supported io6=0 supported io6=1 cache program not supported io7=0 supported io7=1 table 13. the defnition of 4th code of id table defnition information value page size (exclude spare area) 1k-byte io1, io0= 0,0 2k-byte io1, io0= 0,1 4k-byte io1, io0= 1,0 reserved io1, io0= 1,1 size of spare area (byte per 512-byte) 8 io2=0 16 io2=1 sequential read cycle time 50ns io7, io3= 0,0 30ns io7, io3= 0,1 25ns io7, io3= 1,0 reserved io7, io3= 1,1 block size (exclude spare area) 64k-byte io5, io4= 0,0 128k-byte io5, io4= 0,1 256k-byte io5, io4= 1,0 512k-byte io5, io4= 1,1 organization 8-bit io6=0 16-bit io6=1 p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
37 9-1. r/b#: termination for the ready/busy# pin (r/b#) the r/b# is an open-drain output pin and a pull-up resistor is necessary to add on the r/b# pin. the r/b# outputs the ready/busy status of read/program/ erase operation of the device. when the r/b# is at low, the device is busy for read or program or erase operation. when the r/b# is at high, the read/program/erase operation is fnished. figure 22. r/b# pin timing information rp value guidence vcc (max.) - vol (max.) rp (min.) = = 3.2v i ol + il 8ma + il where il is the sum of the input currnts of all devices tied to the r/b pin. rp (max) is determined by maximum permissible limit of tr. considering of the variation of device-by-device, the above data is for reference to decide the resistor value. @ vcc = 3.3 v, ta = 25c, c l =50pf rp (ohm) ibusy ibusy [a] tr, tf [s] tf 002 4.2 150 1.2 50 100 0.8 0.6 1.8 1.8 1.8 1.8 1k 2k 3k 4k m2 n002 m1 n001 tr v ss v cc r/b# rp c l device v cc ready vcc v oh tr tf v ol bu sy v ol p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
38 9-2. power on/off sequence after the chip reaches the power on level (vth = 2.5 v), the internal power on reset sequence will be triggered. during the internal power on reset period, no any external command is accepted. there are two ways to identify the termination of the internal power on reset sequence. please refer to the power on/off sequence waveform. ? r/b# pin ? wait 1 ms during the power on and power off sequence, it is recommended to keep the wp# = low for internal data protection. figure 23. power on/off sequence 2.5 v (vth) vcc wp# we# r /b# 1 ms 1 us (min.) p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
39 9-2-1. wp# signal below fgures show the relationship between wp# signal and the four operations of the enabled/disable program and enabled/disabled erase. tww we# io[7:0] 80h 10h wp# tww we# io[7:0] 80h 10h wp# tww we# io[7:0] 60h d0h wp# tww we# io[7:0] 60h d0h wp# figure 24. enable programming figure 25. disable programming figure 26. enable erasing figure 27. disable erasing p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
40 10. software algorithm 10-1. invalid blocks (bad blocks) the bad blocks are included in the device while it is shipped. during the time of using the device, the additional bad blocks might be increasing; therefore, it is recommended to check the bad block marks and avoid to use the bad blocks. furthermore, please read out the bad block information before any erase operation since it may be cleared by any erase operation. figure 28. bad blocks while the device is shipped, the value of all data bytes of the good blocks are ffh. the 1st byte of the 1st or 2nd page in the spare area for bad block will not be ffh. the erase operation at the bad blocks is not recommended. after the device is installed in the system, the bad block checking is recommended. the fgure shows the brief test fow by the system software managing the bad blocks while the bad blocks were found. when a block gets damaged, it should not be used any more. due to the blocks are isolated from bit-line by the selected gate, the performance of good blocks will not be impacted by bad ones. bad block bad block min typ. max unit remark valid (good) block number 1004 1024 block block 0 is guaranteed to be good up to 1k cycles with 1 bit ecc per 528-byte table 14. valid blocks p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
41 10-2. bad block test flow although the initial bad blocks are marked by the fash vendor, they could be inadvertently erased and destroyed by a user that does not pay attention to them. to prevent this from occurring, it is necessary to always know where any bad blocks are located. continually checking for bad block markers during normal use would be very time consuming, so it is highly recommended to initially locate all bad blocks and build a bad block table and reference it during normal nand fash use. this will prevent having the initial bad block markers erased by an unexpected program or erase operation. failure to keep track of bad blocks can be fatal for the application. for example, if boot code is programmed into a bad block, a boot up failure may occur. the following section shows the recommended fow for creating a bad block table. figure 29. bad block test flow start block no. = 0 create (or update) bad block table read ffh check block no. = 1023 end block no. = block no. + 1 pass yes fail no (note) 10-3. failure phenomena for read/program/erase operations the device may fail during a read, program or erase operation. the following possible failure modes should be considered when implementing a highly reliable system: table 15. failure modes failure mode detection and countermeasure sequence erase failure status read after erase block replacement programming failure status read after program block replacement read failure read failure ecc note: read ffh check is at the 1st byte of the 1st and 2nd pages of the block spare area. p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
42 10-4. program when an error occurs in page a, please re-load the data from the data buffer to re-program data to other good page (e.g. page b) of other good blocks. it is recommended to create the bad block table or other method by system software to avoid using the bad blocks. figure 30. failure modes 10-5. erase when an error occurs during erase operation, it is recommended to create the bad block table or other method by system software to avoid using the bad blocks. block another good block program error occurs in page a buffer memory page b figure 31. program flow chart start sr[6] = 1 ? sr[0] = 0 ? no command 80h set address write data write 10h read status register (or r/b# = 1 ?) program error yes no yes * program command flow program completed p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
43 figure 32. erase flow chart figure 33. read flow chart start verify ecc no command 00h set address read data out ecc generation reclaim the error page read completed yes command 30h sr[6] = 1 ? read status register (or r/b# = 1 ?) no yes host controller ecc handling start sr[6] = 1 ? sr[0] = 0 ? no * * command 60h set block address command d0h read status register (or r/b# = 1 ?) erase error yes no the failed blocks will be identified and given errors in status register bits for attempts on erasing them. erase completed yes p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
44 application notes 1) ready time depends on the pull-up resistor tied to the r/b# pin. 2) no programming is allowed on an un-erased page. if this is done no pgm is performed and a status register is given to the user. user then needs only to choose a different address and not to insert the data again. it is recommended to forbid cosecutive programming on its own controller. p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
45 11. package information p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
46 title: package outline for 63-vfbga (9x11x1.0mm, ball-pitch: 0.8mm, ball-diameter: 0.45mm) p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
47 12. revision history rev. no. descriptions page date 0.01 1. figures 3, 5, 6, 7, 8, 10, 12, 15, 16, 17, 18, 22, 24, modifed p 10, 12 to 14, 16, 17, oct/19/2011 p22 to 25, 31 to 33, 37, 39 to 43 2. chapter 8 & 9: description updated p32, 33 3. table 8. logic & command table modifed p33 0.02 1. "optional code" added in part number all apr/18/2011 2. nop modifed from 8 (main area plus spare area) to 4 p16, 28 3. typical program time modifed from 200us to 250us p4, 28 4. ready/busy pin timing information axis adjustment p37 5. power on timing spec modifed from 2ms to 1ms p38 0.03 1. changed datasheet title to preliminary p4 may/05/2011 0.04 1. o rdering information revised due to part name changed all aug/19/2011 from mx30lf1g08am to mx30lf1g08aa 2. wording-rephrase & capitalization all 3. waveforms adjustment all 4. table 2. vlko specifcations removed p30 0.05 1. rephrased and adjusted waveform sequences all dec/28/2011 2. added "dnu" ball for vfbga p6 3. modifed figure "ac waveform for cache read " p17 4. added the check mark of "acceptable while bus y" for p34 cache read end item in command table 5. added "read failure" in table of failure modes p41 6. marked the vfbga as "advanced information" p4, 5 7. removed "secure otp (optional)" p4 8. removed c grade descripton p4, 5, 29 9. added r/b# timing in power on/off w aveform p38 0.06 1. modifed the vfbga ball-out: h8 from "nc" to "vcc" p6 feb/08/2012 1.0 1. removed "preliminary" from datasheet title p4 jun/04/2012 1.1 1. removed "advanced information" for vfbga package p4, 5 aug/13/2012 1.2 1. content wording rephrased p9, 32, 37, 39, 40, 42 mar/28/2013 2. flow chart modifcations p42,43 1.3 1. added "bad block table build up" descriptions p41 dec/18/2013 1.4 1. changed tclr from 15ns to 10ns p31 feb/27/2014 1.5 1. corrected tals timing waveform as ale high till we# high p18 sep/17/2014 for figure 12. p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa
48 m acronix i nternational c o., l td. http://www.macronix.com macronix international co., ltd. reserves the right to change product and specifcations without notice. except for customized products which have been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applica - tions only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liabil - ity arisen therefrom. copyright? macronix international co., ltd. 2011~2014. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only. for the contact and order information, please visit macronixs web site at: http://www.macronix.com p/n: pm1113 rev. 1.5, sep. 17, 2014 mx30lf1g08aa

▲Up To Search▲

Price & Availability of MX30LF1G08AA-XKI

	To Download MX30LF1G08AA-XKI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .